1. Field of the Invention
The present invention generally relates to processing systems and more particularly to processing systems wherein external memory accessing is required. Still more particularly, the present invention relates to an improved external memory access control for a processing system which reduces power consumption of the processing system by establishing external memory enable time durations which are independent from the external memory accessing rate.
2. Description of Related Art
As discussed in presently pending U.S. patent application Ser. No. 07/569,935, also entitled Improved External Memory Access Control for a Processing System, which application is assigned to the assignee of the present application, processing systems which include at least one microprocessor are well known in the art. In such processing systems, the microprocessor is generally required to access external memory for data and/or instructions. It is also common for microprocessor-based processing systems to have periods of high activity, wherein a large number of operations are performed per unit of time, interspersed with periods of low activity, wherein relatively few operations are performed per unit of time.
To reduce the power consumption of such processing systems during periods of low activity, it has been common in the prior art to reduce the external memory access rate of the microprocessor. This is typically accomplished through the use of either a variable-rate oscillator clock source or by incorporating into the microprocessor a clock divider circuit to reduce the external memory access rate. Since the microprocessor communicates with external memory through a bus, the external memory access rate may also be referred to as a bus access rate.
The foregoing prior art methods of reducing power consumption during low activity periods by reducing the external memory access rate have been generally effective with digital CMOS logic systems because the power consumption of digital CMOS logic systems is roughly proportional to the number of signal transitions occurring per unit of time. This is true because digital CMOS logic consumes the majority of its power when its internal and input signals are changing and, inversely, it consumes very little power when its internal signals are not changing.
Unfortunately, standard commercially available memory devices such as random access memory (RAM) devices and electrically programmable read only memory (EPROM) devices differ from digital CMOS logic in that these devices consume power whenever their enable inputs are held in the active state. The power consumption of such devices is therefore dependent upon the amount of time the memories are enabled (the amount of time the CHIP ENABLE signal is held active) in addition to the memory access rate (the frequency of transitions of the CHIP ENABLE signal). Although it is technically possible to provide RAM and EPROM devices which would consume power only when internal and external signals are in transition, these devices would be more complex and would not benefit from the economics of scale which result from providing one design for all applications.
In existing microprocessor-based processing systems, the CHIP ENABLE signal for external RAM and/or EPROM is decoded either within the microprocessor or by logic external to the microprocessor from bus control signals provided by the microprocessor. Typical bus control signals, as for example with respect to the 8031 class of microcontroller include the address lines, ALE, PSEN*, RD*, and WR*. The names and functions of the bus control signals differ from one microprocessor/microcontroller to another, but the fundamental concept of providing enabling and directional information to devices external to the microprocessor remains the same.
The limitation in the prior art to this application and those related thereto, with respect to low-power processing system operation, is that when the memory access rate of existing microprocessors and controllers is reduced in an attempt to save system power, the width of the bus control signals provided by the microprocessor (the external memory enable time durations) varies in direct proportion to the bus rate (external memory access rate) of the processor. As a result, even though the external memory access rate of the processor is reduced, the external memory enable time durations proportionately increase. Hence, the slower the memory access rate becomes, the longer the external memory enable time durations become. This is wasteful of system power since the external memory devices are enabled for a much longer time duration than is required to complete the accessing of the external memory devices.
U.S. patent application Ser. No. 07/569,935, identified above and incorporated herein by reference, provides a processing system which includes a processor which reduces the power consumption of standard commercially available memory devices which are not specifically designed for very low power. U.S. patent application Ser. No. 07/569,935 provides such a processing system by providing an external memory access control system which renders the external memory enable time durations independent from the number of external memory accesses per unit of time. Although the control system set forth in the related application is effective and useful generally, special characteristics arise in certain applications that can be exploited to create an even simpler control system. The present invention teaches such a control system that can be readily and simply constructed in situations wherein programmable clock speed is available.